IBM does not have a long history in the supercomputing game. Their current technology grew out of a research thrust into computer chess and the machine Deep Blue. IBM coupled their RS/6000 workstations together with a high performance switch and marketed the machine as the SP1 in 1993. The next year, the next generation switch gave rise to the SP2. Since then, IBM has stopped the numerical labels. The SP is more of a machine type than a specific machine. Current SPs may contain one or several different processor types, some of which are single processors, some of which are multiprocessor boards with locally shared memory.
The popular Power2 processor comes in different flavors. The so-called wide node has 256K cache and 256 bits memory bandwidth. The processor has double integer units and double floating point units, both of which execute multiply-and-adds, giving 4 float results per cycle. The Instruction Cache Unit can execute a branch operation and a register operation each cycle, and allows for 8 instructions to be decoded, and 6 issued. Taken together, this yields an 8-flod superscalar speedup. The thin nodes have only 64K cache, and 64 bit memory bandwidth.
The positioning of the SP as a supercomputer, rather than a cluster of RS6000 workstations stems from the high performance switch. Eight switchs form a switch board which connects 4*4 processors. The coupling to a processor is mediated by a PowerPC chip, via the microchannel, so communication is controlled by the CPU itself. There is no autonomous message processor.
The theoretical peak transfer rate of version 3 of the high performance switch is 150Mb/sec bi-directional transfer.